1. Field of the Invention
The present invention relates generally to current reference circuits, and more particularly to current reference circuits that operate at low voltages.
2. Background of the Invention
As complementary metal-oxide-semiconductor (CMOS) technology evolves to lower supply voltages, reference circuits, such as current sources, are required to operate at the lower supply voltages. However, conventional reference circuits (e.g., bandgap generators) typically have poor characteristics or fail to operate at low supply voltages. For example, a conventional bandgap generator having four levels of stacking (e.g., four components between a supply rail and ground), exhibits poor performance when a power supply voltage of about 1.5 volts or lower is employed.
FIG. 1 is a schematic diagram of a first conventional current reference circuit 100 that employs four levels of stacking. With reference to FIG. 1, the reference circuit 100 includes a first p-channel metal-oxide-semiconductor field effect transistor (PFET) 102, a second PFET 104, a first n-channel metal-oxide-semiconductor field effect transistor (NFET) 106, a second NFET 108, a resistor 110, a first diode 112 and a second diode 114. A source of the first PFET 102 and a source of the second PFET 104 are coupled to a rail voltage (VDD). A drain of the first PFET 102 and a drain of the first NFET 106 are coupled together and to a gate of the first NFET 106 and to a gate of the second NFET 108. A drain of the second PFET 104 and a drain of the second NFET 108 are coupled together and to a gate of the first PFET 102 and to a gate of the second PFET 104. A source of the first NFET 106 is coupled to ground via the first diode 112, and a source of the second NFET 108 is coupled to ground via the resistor 110 and the second diode 114. The first and second diodes 112, 114 are selected so as to have areas that differ by a factor of n.
As is known in the art, the feedback loop formed by the PFETs 102, 104 and the second NFETs 106, 108 forces the first diode 112 and the second diode 114 to operate at the same bias current. Accordingly, the reference circuit 100 may serve as a constant current source having an output current (e.g., through the second NFET 108) related to the ratio of the areas of the first and second diodes 112, 114 (e.g., an output current related to a natural log of the factor n). While suitable for supply voltages in excess of about 1.5 volts, the four levels of stacking of the reference circuit 100 are not suitable for use at lower voltages (e.g., as a voltage lower than about 1.5 volts is insufficient to properly bias the transistors and diodes of the reference circuit 100).
FIG. 2 is a schematic diagram of a second conventional current reference circuit 200 that employs three levels of stacking. The second current reference circuit 200 is similar to the first current reference circuit 100 of FIG. 1, but does not employ the first and second diodes 112, 114. In the reference circuit 200 of FIG. 2, the feedback loop formed by the PFETs 102, 104 and the NFETs 106, 108 forces the current through the first and second NFETs 106, 108 to be equal and proportional to the difference between the threshold voltages (VTH) of the first NFET 106 and the second NFET 108 (e.g., IOUT=(VTHN1−VTHN2)/R). While suitable for use with low supply voltages (e.g., due to only three levels of stacking), the current reference circuit 200 requires the use of transistors having multiple threshold voltages (e.g., requiring multiple and precise implant doses during device manufacture, and increasing manufacturing time and cost).
FIG. 3 is a schematic diagram of a third conventional current reference circuit 300 that also employs three levels of stacking. The third current reference circuit 300 is similar to the second current reference circuit 200 of FIG. 2, but employs NFETs implemented using p-well technology (e.g., the first and the second NFETs 106, 108 employ body contacts). The same channel length is employed for each of the first and second NFETs 106, 108, but differing channel widths are used (e.g., creating a resistance differential between the first and second NFETs 106, 108 that behaves similarly to the resistor 110 of the first conventional reference circuit 100 of FIG. 1). The body contacts of both the first and the second NFETs 106, 108 are grounded. Additionally, a resistor 116 is coupled between the source of the first NFET 106 and ground.
In the reference circuit 300 of FIG. 3, the feedback loop formed by the PFETs 102, 104 and the NFETs 106, 108 forces the current through the first and second NFETs 106, 108 to be equal and proportional to the difference between the threshold voltages (VTH) of the first NFET 106 and the second NFET 108 (e.g., IOUT=(VTHN1−VTHN2)/R. The voltage drop across the resistor 116 produces an equivalent voltage drop across the body-source regions of the first NFET 106 so as to increase the threshold voltage of the first NFET 106. While suitable for use at low supply voltages (e.g., due to only three levels of stacking), the current reference circuit 300 requires the use of p-well technology (increasing manufacturing time and cost).
Accordingly, a need exists for improved methods and apparatus for generating a current reference when low supply voltages are employed.